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Hello,In MPSM entry with PDA mode, which exits first?  MPSM or PDA?Thanks in advance!Continue

Started Jan 31

DFI data width
1 Reply

Hello, I'm new to this topic.Can you tell me why dfi write data bus width is generally twice the width of DRAM data bus? Is this because of the double data rate(DDR)?Continue

Started this discussion. Last reply by John MacLaren Jan 24.

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John MacLaren replied to Prateek's discussion DFI data width
"Hi Prateek, Yes, the DFI data bus bandwidth matches the bandwidth of the memory data bus.  For a matched frequency controller and PHY and DDR memory, the DFI data bus is 2X the width of the the memory data.  If the controller clock is 1/2…"
Jan 24
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Jan 23

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