The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices.
The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries.
DFI Group Releases Initial Version of the DFI 5.0 Specification
for High-Speed Memory Controller and PHY Interface
AUSTIN, Texas, May 2, 2018 — The DDR PHY Interface (DFI) Group today released version 5.0 of the specification for interfaces between high-speed memory controllers and physical (PHY) interfaces to support the requirements of future mobile and server memory standards. The DFI specifications, widely adopted throughout the memory industry, enable greater interoperability.
The DFI Group included several interface improvements in this newest specification. The new version of the specification adds protocol support for the newest DDR and low-power memory technologies. Previous versions of the specification defined memory training across the interface between the memory controller and the PHY. The new specification completely transitions to PHY-independent training mode where the PHY trains the memory interface without involving the controller. Other interface improvements include lower power enhancements, providing a PHY-independent boot sequence, expanding frequency change support, and defining new controller-to-PHY interface interactions.
“The industry is beginning to embrace new low-power and DDR memory technologies, including high-performance devices such as servers, storage, and networking; autonomous vehicles; and low-power handheld devices and IoT,” stated John MacLaren, DFI Group chairman and Cadence design engineering architect. “The DFI Group, consisting of experts from leading companies in the industry, is enthusiastic to contribute to enabling this transition with the latest release of the DFI specification. Beyond supporting the latest DDR and LPDDR memory technologies, we have introduced significant improvements to the interface to improve low power, interoperability, and interface interactions.”
“Adopting open and standard interfaces like the new DFI 5.0 specification for high-speed memory controller and PHY interface allows AMD to efficiently and effectively adopt new memory standards as we deliver high-performance products to our customers. AMD is pleased to contribute to the DFI 5.0 standard and push for interoperability.”
“Cadence has been a key contributor to the DFI 5.0 standard, which helps to ensure interoperability between DDR PHYs and DDR controllers, particularly for future memory devices,” said Marc Greenberg, group director, product marketing, DDR, HBM, flash/storage and MIPI IP. “Cadence customers and partners using DFI 5.0 can be confident in having a defined interoperability standard between their DDR PHYs and DDR controllers, whether the PHY and controller come from Cadence, internal development at the Cadence customer, or a third party.”
“As a leading provider of DDR IP and Verification IP, Synopsys makes significant investments to ensure that our DesignWare® controller and PHY IP are compliant to industry standards such as DFI,” said Navraj Nandra, Sr. Director of Marketing for Interface and Analog IP solutions at Synopsys. “By being a long-term contributor and implementer of the DFI interface through many DDR and LPDDR generations, including DDR5/LPDDR5, Synopsys understands the importance of supporting the latest DFI standards to help designers ease their integration effort and reach their memory performance requirements.”