DFI - ddr-phy.org

DFI Contributors

 

 

Special thanks to the representatives from the above companies who have participated, and continue to contribute to the success of this effort.

 

About DFI (DDR PHY Interface)

... Simplify DDR PHY

The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices.


The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries.


Learn more about DFI here ...

DFI News

DFI Group Releases Final Version DFI 3.1 and Preliminary DFI 4.0 Addendum of its High-Speed Memory Controller and PHY Interface Specification

San Jose, CA , April 8th: Today the DDR PHY Interface (DFI) Group, consisting of leading IP and product companies including ARM, Cadence, Intel, LSI, Samsung, ST and Synopsys, released the final version of the DFI 3.1 specification.

The standard defines an interface protocol between DDR memory controllers and PHY interfaces. It is intended to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices. The standard replaces the preliminary DFI 3.1 specification which was available since mid 2012.

In addition the group released a new – preliminary – DFI 4.0 addendum specifically addressing the requirements to support LPDDR4 memories.

The DFI 4.0 addendum includes the following features:

  • Necessary command interface signaling and timing changes to support all LPDDR4 memory commands
  • New channel architecture defined on DFI interconnect to align with the LPDDR4 channel architecture.
  • CA training extensions necessary to extend the existing CA training to support LPDDR4.
  • Changes to Read Data Eye Training and Write Leveling to accommodate differences in LPDDR4 training definitions.
  • Addition of Write DQ training for LPDDR4 and extended to all other memory classes.
  • Addition of DB training to support DDR4 data buffer training.
  • Addition of Geardown support.
  • Modifications of DFI specific features and definitions including
    1. new slice width parameter
    2. modified data chip select definition
    3. new PHY master handshake protocol
    4. new frequency value indicator
    5. new DFI disconnect protocol
    6. modified data bit disable function.

“Mobile consumer devices continue to demand both increased memory performance and power efficiency, requiring the use of the latest available technologies like LPDDR4 memory”," said John MacLaren, Senior Member of Consulting Staff at Cadence Design Systems and chairman of the DFI Group. "We are excited to add LPDDR4 mobile memory support to the DFI standard, enabling the benefits of this technology for the rapidly growing mobile computing market.”

Both the final DFI 3.1 specification as well as the DFI 4.0 addendum is available now for download at www.ddr-phy.org

 
 
 

Latest Activity

Stephen Bond replied to Stephen Bond's discussion Naming of dfi_wrdata_cs(_n)
"Hi John, Many thanks for your quick response.  Just to clarify: you say there is no plan to change the polarity of these signals. Does that mean that the correct names continue to be dfi_wrdata_cs_n and dfi_rddata_cs_n.  (i.e. the name…"
yesterday
John MacLaren replied to Stephen Bond's discussion Naming of dfi_wrdata_cs(_n)
"Hi Stephen, Despite the name change of dfi_cs and polarity change for LPDDR4, there is no plan to change the polarity of the dfi_wrdata_cs_n and dfi_rddata_cs_n at this time; although the topic has been raised regarding what would be the most…"
yesterday
Kamlesh Mulchandani replied to Kamlesh Mulchandani's discussion Training during normal operation.
"Hi John, When we do training during normal operation, it should be periodic training(Not full length training). Is that correct? So what should be maximum duration for both types? Thanks."
Tuesday
Kamlesh Mulchandani replied to Kamlesh Mulchandani's discussion Refresh during clock disable?
"Hi John, Thanks for getting back in time. We are waking up from power down when refresh command is sent to DRAM memory. On a different note, this post is taken from DDR-PHY, 4.7 DFI Clock Disabling, "If the system requires the clocks of the…"
Tuesday

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