DFI - ddr-phy.org

DFI Contributors

 

Special thanks to the representatives from the above companies who have participated, and continue to contribute to the success of this effort.

 

About DFI (DDR PHY Interface)

... Simplify DDR PHY

The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices.


The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries.


Learn more about DFI here ...

DFI News

DFI Group Releases the 2nd Revision of the DFI 4.0 Addendum to its High-Speed Memory Controller and PHY Interface Specification

San Jose, CA , March 30, 2015: Today the DDR PHY Interface (DFI) Group, consisting of leading IP and product companies including ARM, Avago, Cadence Design Systems, Intel, Samsung, ST, Synopsys, and Uniquify, released the 2nd revision of the DFI 4.0 addendum to the DFI Specification.

The standard defines an interface protocol between DDR memory controllers and PHY interfaces. It is intended to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices. The addendum supplements the DFI 3.1 specification released in April 2014. The DFI 4.0 addendum specifically adds support of LPDDR4 memories and extends DDR4 support for RDIMM and LRDIMM, as well as enhancing DFI specific features.

The DFI 4.0 addendum includes the following features:

  • Necessary command interface signaling and timing changes to support all LPDDR4 memory commands
  • New channel architecture defined on DFI interconnect to align with the LPDDR4 channel architecture.
  • CA training extensions necessary to extend the existing CA training to support LPDDR4.
  • Changes to Read Data Eye Training and Write Leveling to accommodate differences in LPDDR4 training definitions.
  • Addition of Write DQ training for LPDDR4 and extended to all other memory classes.
  • Addition of DB training to support DDR4 data buffer training.
  • Addition of Geardown support.
  • Addition of 3D Stack (3DS) support.
  • Modifications of DFI specific features and definitions including

    1. new PHY master handshake protocol
    2. new frequency signal
    3. new DFI disconnect protocol
    4. new DFI feature and memory topology matrix
    5. new slice width parameter
    6. new inactive chip select definition
    7. modified data chip select definition
    8. modified data bit disable function
    9. modified DFI training to be an optional feature
    10. modified the update interface regarding self refresh.

“The industry validated the value of LPDDR4 with strong adoption by incorporating the standard into many leading edge devices in 2014, and there is increasing momentum in 2015. The DFI 4.0 enhancements extend the DFI specification to ensure that DDR IP users have a path to interoperability between LPDRR4 controller and PHY IP," said John MacLaren, DDR Controller IP Architect at Cadence and chairman of the DFI Group. "Finalization of the addendum enables the community to expand use of LPDDR4 mobile memory and ensure interoperability for these new features.”

The DFI Group also welcomes our newest members, Uniquify and Avago (via LSI acquisition), and thanks them for their contributions to the development of the DFI standard.

The DFI 4.0 addendum version 2 is available now for download at
www.ddr-phy.org.
 
 
 

Latest Activity

John MacLaren replied to Nishant Patel's discussion DFI & HBM
"Hi Nishant, DFI does not currently have HBM support. Thanks, John"
yesterday
Profile IconMatt Moe, Srinivas Akula, Hakee, Ahn and 1 more joined DFI - ddr-phy.org
yesterday
Profile IconSandra Weber, Sachin Jadhav, Adrian Nunez and 11 more joined DFI - ddr-phy.org
Monday
Alexander Holland replied to Patrick Twomey's discussion dfi_wrdata_mask polarity for DDR3 vs DDR4 - DFI 3.0 onwards
"Is this still true? The DFI v3.1 specification does not have this clarification added to table 6."
Jul 21

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