The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices.

The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries.

DFI Group Releases Version 3.1 of Its High-Speed Memory Controller and PHY Interface Specification

New Version Includes Support for LPDDR3 Memory for Smartphones and Tablets


SAN JOSE, CA--(Marketwire - May 29, 2012) : The DDR PHY Interface (DFI) Group today released the DFI 3.1 specification, the latest version of the pervasive industry specification that defines an interface protocol between DDR memory controllers and PHYs. The specification enables the development of systems-on-chip (SoCs) that support the DDR3 and DDR4 memory standards. Version 3.1 adds support for the LPDDR3 mobile memory standard for smartphones and tablets, as well as enhancements to the low-power interface and training features. The DFI interface standard was developed through the collaborative effort of leaders in the semiconductor and EDA markets and has become the de facto industry standard for high-bandwidth memory interfaces.

"Consumer mobile electronics continue to demand both increased memory performance and power efficiency, requiring the use of new technologies such as LPDDR3 memory," said John MacLaren, chairman of the DFI Group. "We are excited to add LPDDR3 mobile memory support to the DFI standard as it means the benefits of this technology will now be available to the rapidly growing mobile computing market."

The preliminary DFI 3.1 memory specification is available now for download at www.ddr-phy.org.

About the DFI Group
The DFI Group is a standards organization comprised of leading semiconductor companies that implement the DFI specification. Current member companies include ARM, Cadence, Intel, LSI, Samsung, ST and Synopsys. The specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, its community, activities and how to participate, visit: www.ddr-phy.org.

What Member Companies are Saying about the DFI 3.1 Specification:
"It is vital to our customers' success that we continually innovate to take advantage of both enhancements in the underlying memory technology and advances in IP implementation," said Marc Greenberg, product marketing director, SoC Realization Group, Cadence. "At Cadence we have been at the forefront of supporting advanced memory standards like LPDDR3 and DDR4 to deliver industry leading power and performance. The latest additions to the DFI standard allow us to continue to do so while reducing design risk and reducing the cost of design integration."

"The addition of LPDDR3 within the DFI specification enables Synopsys to extend our support of the latest low-power DRAM protocols for smartphone and tablet applications," said Navraj Nandra, senior director of marketing for mixed-signal and analog IP at Synopsys. "As a leading DDR IP provider, our active participation in the DFI committee helps to ensure that DesignWare® IP supports the latest DDR technologies so our customers can continue to meet their SoCs' power, performance and latency goals while reducing integration effort and risk."

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
dsolov@cadence.com (e-mail)
408-944-7226 (phone)

Cadence is a registered trademark of Cadence Design Systems, Inc. in the United States and other countries. Synopsys and DesignWare are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.