Hi,DFI specs 5.0 is not clear to me in mapping CA bus onto DFI address for DDR5,What I found so far is the following: "For low power memories and the latest DDR DRAMs, the CA bus is mapped onto to…Continue
Started this discussion. Last reply by Mohamed Rayan Apr 8.
PDA(Per DRAM addressability) is DDR4 feature which has the following specifications:Enable PDA mode using MR3 bit “A4=1”.In the ‘per DRAM addressability’ mode, only MRS commands are allowed.The mode…Continue
Started this discussion. Last reply by John MacLaren Nov 17, 2017.
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