Information about tPHY_RDLAT

Hi,

I wanted to know if tPHY_RDLAT should be a fixed number and can be defined as a range.

Thanks,

Vikas

▶ Reply to This

Replies to This Discussion

Permalink Reply by MC_DGN on June 11, 2012 at 10:43pm

Also when PHY sends dfi_rdaata_vld signal, what is the need to define such parameters?

▶ Reply

Permalink Reply by John MacLaren on June 12, 2012 at 7:55am

Hi Vikas,

tPHY_RDLAT, the timing parameter that specifies the time from dfi_rddata_en to dfi_rddata_valid, is specified as a maximum timing constraint. Therefore, any delay <= tPHY_RDLAT is an acceptable value. Since this timing is dependent on the loop time through the PHY, out to DRAM, and back - it is generally expected that the timing may have some variation.

Thanks...JOHN

▶ Reply

Permalink Reply by MC_DGN on June 16, 2012 at 12:24am

Thanks for the reply John.

If dfi_rddata_vld does not goes high from PHY in tPHY_RDLAT clock cycles memory controller can Flag a error.