The DFI spec does not specify about the phase encoding in detail for 1:2 and 1:4 systems . Is there any addendum document or any other articles which talk of the phase encoding in detail?
The DFI Specification has a section, "Frequency Ratios Across the DFI", that discusses this topic - section 4.10 of DFI 5.0 Specification. In general, the frequency ratio sends multiple clock cycles of information on a single DFI clock to a PHY that is operating at a higher frequency; this information is sent per phase. Please provide a specific example if you need more explanation.