Denali Databahn - DDR Hard PHY

Databahn™ DDR Hard PHY
The DFI-compliant Denali Hard PHY IP block is a complete GDSII solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each PHY is delivered to match the unique requirements of the customer's DDR application.

Using Denali's Hard PHY reduces risk and time-to-market for deploying memory interfaces in silicon. The PHY is configurable for data width, ECC, low power, and many other options. DDR1/2/3 and LPDDR1/2 devices are also supported.

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