DFI - ddr-phy.org

Ramy Ahmed Ali
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Ramy Ahmed Ali's Discussions

LPDDR5 write interleaving feature

There is a special case write in the LPDDR5 DDR standard which requires insertion of a gap at the middle of the burst 32 write like the following diagram from the LPDDR5 standard.The question here,…Continue

Started Apr 1

DFI 5.0 read and write interface signaling and their clock domains
1 Reply

Hi,I would like to ask about the write/read interface signals (like "dfi_wrdata_en_p0,1,2,3") as they are synced to the DFI clock as per my understanding to the Ch.4 Functional use write/read…Continue

Started this discussion. Last reply by John MacLaren Mar 6.

DFI training in 5.0
1 Reply

Hello,I am wondering why the training interface is removed in the latest DFI 5.0 specs. It is mentioned in the release information that the training become optional. And in the phy boot sequence, the…Continue

Started this discussion. Last reply by John MacLaren Nov 12, 2018.

Read data rotation inquiry
2 Replies

Hi, I have a question regarding the Read data rotation.First example, when first word…Continue

Started this discussion. Last reply by Ramy Ahmed Ali Jan 17, 2017.

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