John MacLaren's Page

"Hi Sai, The tCMD_LAT timing parameter in DFI correlates directly with the CAL Mode (CS_n to Command Address latency)  of DDR4.  Since the DRAM timing is set by an MRS; it would seem logical that the setting would remain static during…"

"Hi Gyan, In regards to the assertion of dfi_lp_req, I have always associated the assertion with memory being in a low power state which would generally imply that memory transactions are complete.  Additionally, the PHY can wait for any traffic…"

"Hi Gyan, This is illegal, see below, page 124 of the DFI 3.0 Specification: "Once the dfi_lp_req signal is de-asserted, the PHY must return to normal operating mode within the number of cycles indicated by the dfi_lp_wakeup signal." In…"

"Hi Qiannan, You are correct, the figure is wrong.  The signal dfi_rddata_en_p0 should be shifted by 1 DFI clock to the right.  Also, please note my previous discussion "1:2 Frequency Ratio Figures PHY timing is misleading" which…"

"Hi Patrick, In Figure 33, tWRDATA_DELAY begins following tPHY_WRLAT, that is on the first clock where dfi_wrdata_en is asserted.  So even though this aligns with the beginning of the dfi_wrdata, I believe the timing is correct. Thanks, John…"

"Hi Varma, You are correct.  In general, dfi_reset_n is only necessary when the corresponding RESET# on the DRAM interface.  So the note in Figure 1 should be note 9 rather than note 6. Thanks, John MacLaren"

"Hi Varma, In general I would expect a copy of dfi_wrdata_cs_n and dfi_rddata_cs_n to be sent to each individual data slice of the PHY in the same way that dfi_rddata_en and dfi_wrdata_en are replicated per slice.  Therefore the definition of…"

"Hi Srinivas, The dfi_phy_wrlvl_cs_n signal is sent from the PHY to the MC to indicate which chip select the PHY is requesting to be trained.  This signal is optional to support for the PHY, the PHY is not required to request training nor to…"

"Srinivas, The signal name in the specification is incorrect, it should read "The MC transfers the dfi_rddata_cs_n signal to identify the chip select currently being trained."  Thank you for pointing this out.   Sincerely, John…"

"Hi Stephen, I agree, the units should be DFI PHY clocks.  In a frequency ratio system, the adjustment of the signals is done in the PHY and should have a granularity of a single memory clock cycle. Thanks, John MacLaren"

"Hi Vikas, For phydbi_mode=1, the PHY is handling the DBI read and write data inversion including the memory data bus inversion signal (DBI); the MC is not involved in the DBI signaling.  Therefore, the dfi_wrdata_mask signal, which is driven by…"

"The dfi_wrdata_mask signal should be a pass through to the DM pin from the PHY’s perspective.  So the MC is responsible for making certain that the signal’s polarity on the DFI bus matches that of the memory bus.  This is not…"

"Hi Vikas, tPHY_RDLAT, the timing parameter that specifies the time from dfi_rddata_en to dfi_rddata_valid, is specified as a maximum timing constraint. Therefore, any delay <= tPHY_RDLAT is an acceptable value. Since this timing is dependent on…"

"Several people have had issues unzipping the DFI 3.0 and DFI 3.1 Specifications.  The zip file apparently requires Winzip; the standard unzip command under Windows cannot unzip the file.  I will see if this can be resolved.  In the…"

"Several people have had issues unzipping the DFI 3.0 and DFI 3.1 Specifications.  The zip file apparently requires Winzip; the standard unzip command under Windows cannot unzip the file.  I will see if this can be resolved.  In the…"

"Hi Magnus, I am sorry to hear you had difficulty downloading the Specification using Firefox with Linux.  I also use Firefox (not with Linux) and have not had any difficulty.  I will file a ticket with the website support to see if they…"