The width of the signal should be the same as the number of CS pins - 4 in your example. I don't agree that figures 15 and 29 are using enumerated values - both figures show a 2 bit dfi_wrdata_cs_n and dfi_rddata_cs_n value - so…"
1. tPHY_RDLAT is a max timing parameter, so the time from dfi_rddata_en to dfi_rddata_valid can be different from one read to the next or even within a single read data transfer; this accounts for possible time domain crossing that occurs…"
"1. Sounds correct.
2. Sounds correct.
3. dfi_rddata_valid will be asserted for the same number of clocks as dfi_rddata_en; how it is generated by the PHY is determined by the design of the PHY. The signals are not necessarily asserted the…"
For Q1, I am not following your notation "64(8*n)", you will need to clarify.
For Q2, I am assuming we are connecting 2 devices, an MC and a PHY to the DFI bus. The 2 devices will not always have identical signals.…"
"The MC should not be sending write commands on DFI clocks 0, 1 and 2 to the PHY if the write data requires 4 DFI clocks to transfer the write data on the DFI; the commands spacing on DFI should be equivalent to the command spacing on the memory bus.…"
"In the DFI 3.1 Specification section 18.104.22.168 says:
"In a system supporting dynamic burst lengths and BC4, the PHY can use the width of the dfi_wrdata_en_pN signal to determine whether a transfer is a burst of 8 or whether the transfer is a BC4…"
Common uses of the DFI PHY Update are PHY calibration and training sequences. DFI 3.1 added a new PHY independent training handshake that is better suited for this purpose. For example, a PHY may assert dfi_phyupd_req to do an…"
1. dfi_wrdata_en is defined as a single signal replicated across slices, so the interface does not permit driving the signal to some slices and disabling others. So the mask signal is required to mask write data per slice.
The dfi_wrdata_en signal width correlates with the data transfer and does not include the pre- and post-amble clocks. The PHY must account for the additional delays. So, for example, the MC may be programmed to drive…"
1. The MC drives dfi_ctrlupd_req high when the DFI bus is idle to provide an opportunity for the PHY to execute an operation that requires DFI to be idle. For example, this might be when the PHY updates DLL values that may glitch…"
The signal dfi_reset_n has a width defined by the variable "DFI Chip Select Width" - defined in the glossary as "The number of chip select bits on the DFI interface. This is generally the same number of bits as the…"
1. The WE signal could, in theory, be used by the PHY to transfer write data. However, the PHY would basically use WE and WRLAT to generate an internal signal similar to dfi_wrdata_en. So dfi_wrdata_en is provided on the…"
The dfi_wrdata_en signal is connected to the PHY data slices and communicates when and how much write data is transferred on the DFI bus. The dfi_we_n signals is connected to the PHY control logic and is part of the command.…"
Section 4.1 Initialization states:
"The DFI signals that communicate commands or status ... must maintain their default value until the dfi_init_complete signal is asserted."
This statement is applicable to all DFI signals -…"
Signals such as dfi_wrdata_en, dfi_rddata_en are multi-driven signals (identically driven) and fanned-out for ease of connection. These signals should ideally be 1 per PHY data slice regardless of PHY data slice width, so for x4…"