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Dongha Kim
  • Korea, Republic of
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Dongha Kim's Discussions

Two questions about Read Data Interface and Update Interface
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Hello. I have an questio while designing PHY checking the DFI 5.0.1) Seeing Figure 49, the values in PHY dfi_rddata are D0, D1, D2, D3, D4, D5 in order.However, If you refer to dfi_rddata_wN above, I…Continue

Started this discussion. Last reply by Dongha Kim Mar 27.

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Leo Park left a comment for Dongha Kim
"Welcome, Dongha~"
Mar 31
Dongha Kim replied to Dongha Kim's discussion Two questions about Read Data Interface and Update Interface
"+ 1 more question. What does the fsp(frequency set point) mean?? "
Mar 27
Dongha Kim replied to Dongha Kim's discussion Two questions about Read Data Interface and Update Interface
"Thank you for your kind answer.I have a question about your answer. Seeing Figure 49, there is D2 signal in PHY dfi_rddata while "DFI PHY clock phase 0" However, I thought D2 signal have to in phase 2. What's wrong…"
Mar 27
John MacLaren replied to Dongha Kim's discussion Two questions about Read Data Interface and Update Interface
"Hi Dongha Kim Figure 49 illustrates the rotational order in which read data is sent across DFI on the dfi_rddata_w* data busses.  As defined by the DFI specification, read data will rotate around the DFI words; in the figure, since the last…"
Mar 27
Dongha Kim is now a member of DFI - ddr-phy.org
Mar 25

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Company
Samsung
Title
PHY Design
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The Connection with PHY

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At 11:04pm on March 31, 2019, Leo Park said…

Welcome, Dongha~

 
 
 

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