DFI - ddr-phy.org

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Denali Databahn - DDR Hard PHY

Databahn™ DDR Hard PHY

The DFI-compliant Denali Hard PHY IP block is a complete GDSII solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each PHY is delivered to match the unique requirements of the customer's DDR application.



Using Denali's Hard PHY reduces risk and time-to-market for deploying memory interfaces in silicon. The PHY is configurable for data… Continue

Posted on October 8, 2008 at 2:00pm

Denali Databahn - Configurable Memory Controller

Databahn™ DRAM Memory Controller IP

Databahn is the most widely used DDR controller solution, providing the optimal interface between IC designs and the DRAM memory devices. Databahn is fully configurable for performance, power, gatecount, and multi-port data arbitration, and includes an integrated DFI-Compliant PHY.



Databahn supports all commercial DRAM devices including: SDR, DDR1, DDR2, DDR3,… Continue

Posted on October 7, 2008 at 10:00pm

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At 11:55pm on August 19, 2009, Sunil Budumuru said…
Can anyone suggest the DFT (design for testability) techniques for DDR?
 
 
 

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