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Databahn™ DDR Hard PHY

The DFI-compliant Denali Hard PHY IP block is a complete GDSII solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each PHY is delivered to match the unique requirements of the customer's DDR application.



Using Denali's Hard PHY reduces risk and time-to-market for deploying memory interfaces in silicon. The PHY is configurable for data… Continue

Databahn™ DRAM Memory Controller IP

Databahn is the most widely used DDR controller solution, providing the optimal interface between IC designs and the DRAM memory devices. Databahn is fully configurable for performance, power, gatecount, and multi-port data arbitration, and includes an integrated DFI-Compliant PHY.



Databahn supports all commercial DRAM devices including: SDR, DDR1, DDR2, DDR3,… Continue