DFI - ddr-phy.org

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suggestion required with gaining Pre Requisite knowledge

Hi everyone, I am a beginner and I want to learn more about memory controller and PHY to understand the channel interface  can some one sug…

Started by Venkat Naveen Masina

1 May 15, 2018
Reply by Wade Thoenes

DDR5 and LPDDR5 DFI Specs

Hello, Is there any updates related to DFI specifications for LPDDR5 or DDR5? Thanks in advance, Mohamed

Started by Mohamed Rayan

3 Jan 31, 2018
Reply by John MacLaren


Is there any plan to support DFI-HBM??

Started by Naveenkumar

1 Jan 18, 2018
Reply by John MacLaren

DFI 2.1.1/3.- Read Transaction

I have a simple question for the DFI 2.1.1 interface that applies also to the DFI 3.0. In a DDR2 or DDR3 read transaction where the MC tri…

Started by Onoufrios

2 Nov 20, 2017
Reply by Onoufrios

Mapping DDR4 PDA to DFI

PDA(Per DRAM addressability) is DDR4 feature which has the following specifications: Enable PDA mode using MR3 bit “A4=1”. In the ‘per DRA…

Started by Mohamed Rayan

1 Nov 17, 2017
Reply by John MacLaren

Read Training in PHY

Hi, When we are performing the write training i.e write leveling, the delays are adjusted by the PHY based on the data that is given by the…

Started by Saurabh Gupta

0 Oct 5, 2017

Width of dfi_wrdata in case of ECC

In normal scenario i.e without ECC, the width of the dfi_wrdata is 128. Now as we have a support for ECC then should we change the width to…

Started by Sarthak Saxena

1 Oct 5, 2017
Reply by John MacLaren

Support for upcoming DRAM technologies (DDR5)

When will the DFI specification be released to support the upcoming DDR5 technology? Thanks.

Started by Jim Magro

2 Jul 30, 2017
Reply by Mohamed Rayan

definition of dfi_phyupd_type is not clear

by reviewing all DFI spec version from 1.0 to 4.0, I can't find a clear definition of dfi_phyupd_type. Spec said there are 4 types of them,…

Started by Xiaohui Wang

2 Jul 16, 2017
Reply by Xiaohui Wang

4.8 section Frequency ratio across DFI (DFI spec 3.1)

Scenario :PHY frequency in case of 1:2(DFI:PHY or DDR) is twice of the DFI clock. Spec says as PHY operates on higher frequency , MC has op…

Started by Maitri Thakkar

1 May 11, 2017
Reply by John MacLaren


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