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Two questions about Read Data Interface and Update Interface

Hello. I have an questio while designing PHY checking the DFI 5.0.

1) Seeing Figure 49, the values in PHY dfi_rddata are D0, D1, D2, D3, D4, D5 in order.

However, If you refer to dfi_rddata_wN above, I think PHY dfi_rddata should be in order D0, D1, Blank, Blank, D4, D5, D2, D3. Isn't it wrong??

2) The spec. question about Update Interface.

I know that dfi_ctrlupd_ack is not an essential signal. Then, without dif_ctrlupd_ack, how can Memory controller-initiated update activate?? I wonder if there is a Spec for this situation(No dfi_ctrlupd_ack signal forever)

Thanks.

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Hi Dongha Kim

Figure 49 illustrates the rotational order in which read data is sent across DFI on the dfi_rddata_w* data busses.  As defined by the DFI specification, read data will rotate around the DFI words; in the figure, since the last data (D1) is sent on dfi_rddata_w1 in the preceding cycle, the next data (D2) is sent on dfi_rddata_w2 and the subsequent data (D3, D4, D5) are sent rotationally on the other words - dfi_rddata_w3, dfi_rddata_w0, and dfi_rddata_w1, respectively.

For dfi_ctrlupd_req, there is a minimum assertion time defined.  If the controller can complete the operation requested within this minimum time, then the update can be executed without the need for the ACK.  This is often the case for a periodic DLL update which may only require a few clocks to complete.  If a longer time is needed to complete the operation, then the ACK is required.

Thanks,

John

Thank you for your kind answer.
I have a question about your answer.

Seeing Figure 49, there is D2 signal in PHY dfi_rddata while "DFI PHY clock phase 0"

However, I thought D2 signal have to in phase 2.

What's wrong in this question??

Thanks.
 
John MacLaren said:

Hi Dongha Kim

Figure 49 illustrates the rotational order in which read data is sent across DFI on the dfi_rddata_w* data busses.  As defined by the DFI specification, read data will rotate around the DFI words; in the figure, since the last data (D1) is sent on dfi_rddata_w1 in the preceding cycle, the next data (D2) is sent on dfi_rddata_w2 and the subsequent data (D3, D4, D5) are sent rotationally on the other words - dfi_rddata_w3, dfi_rddata_w0, and dfi_rddata_w1, respectively.

For dfi_ctrlupd_req, there is a minimum assertion time defined.  If the controller can complete the operation requested within this minimum time, then the update can be executed without the need for the ACK.  This is often the case for a periodic DLL update which may only require a few clocks to complete.  If a longer time is needed to complete the operation, then the ACK is required.

Thanks,

John

+ 1 more question.

What does the fsp(frequency set point) mean??
 
John MacLaren said:

Hi Dongha Kim

Figure 49 illustrates the rotational order in which read data is sent across DFI on the dfi_rddata_w* data busses.  As defined by the DFI specification, read data will rotate around the DFI words; in the figure, since the last data (D1) is sent on dfi_rddata_w1 in the preceding cycle, the next data (D2) is sent on dfi_rddata_w2 and the subsequent data (D3, D4, D5) are sent rotationally on the other words - dfi_rddata_w3, dfi_rddata_w0, and dfi_rddata_w1, respectively.

For dfi_ctrlupd_req, there is a minimum assertion time defined.  If the controller can complete the operation requested within this minimum time, then the update can be executed without the need for the ACK.  This is often the case for a periodic DLL update which may only require a few clocks to complete.  If a longer time is needed to complete the operation, then the ACK is required.

Thanks,

John

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