In DDR4, Data Mask (DM) polarity has inverted in comparison to DDR2/DDR3, hence it becoming DM_n in DDR4 JEDEC spec.
But this has not been reflected/mentioned in dfi_wrdata_mask definition in DFI 3.0.
Concern is that a MC may implement dfi_wridata_mask one way, a PHY another, causing issues. Especially a concern for a MC/PHY that supports both DDR3 and DDR4.
Clarifications is sought for normal mode and DBI mode.
The dfi_wrdata_mask signal should be a pass through to the DM pin from the PHY’s perspective. So the MC is responsible for making certain that the signal’s polarity on the DFI bus matches that of the memory bus. This is not clear from the DFI specification. the following statement will be added to the signal description in table 6 of the DFI 3.0 Spec:
“The dfi_wrdata_mask polarity should match the polarity of the DRAM bus. For the DRAM Data Mask, for high active DM signal, dfi_wrdata_mask=1 will mask the corresponding write data byte. For low active DM_n, dfi_wrdata_mask=0 will mask the corresponding write data byte. Similarly, for the DRAM Data Bus Inversion, when DBI mode is enabled, for high active DBI signal, dfi_wrdata_mask=1 will indicate data byte inversion. For low active DBI_n, dfi_wrdata_mask=0 will indicate data byte inversion.”
Similar statements will be added for DBI description.
Thanks for pointing this out.