The following signals are listed in the DFI 5.0 specification as being required for DDR5 but it is not obvious what they would map to on the DRAM interface as it uses a
Also, DDR5 has a
CAI input for Command & Address Inversion but there is no obvious DFI signal to drive this. Would it be safe to assume that a signal might be added of the form
dfi_cai_pN or would it be driven from an existing DFI signal?
I presume this is all due to the flux of the DDR5 specification and will be clarified in the DFI specification once it is finalised.