Hello, I'm new to this topic.
Can you tell me why dfi write data bus width is generally twice the width of DRAM data bus? Is this because of the double data rate(DDR)?
Yes, the DFI data bus bandwidth matches the bandwidth of the memory data bus. For a matched frequency controller and PHY and DDR memory, the DFI data bus is 2X the width of the the memory data. If the controller clock is 1/2 the frequency of the PHY clock, then the DFI data bus is 4x the width of the memory data. And so on.