DFI - ddr-phy.org

Definition of tphy_wrlat for multi-cycle commands and/or 2N mode

The definition of tphy_wrlat is specified as:

This parameter specifies the number of DFI PHY clock cycles from the time that a write command is sent on the DFI command interface and when the dfi_wrdata_en signal is asserted.

For the case where the command is multi-cycle and/or memory is operating in 2N mode, when is tphy_wrlat measured from?

Is it from the final cycle of the command or the first cycle with CS asserted?

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