DFI specs 5.0 is not clear to me in mapping CA bus onto DFI address for DDR5,
What I found so far is the following:
"For low power memories and the latest DDR DRAMs, the CA bus is mapped onto to the dfi_address bus"
Does this mean that CA bus is mapped to dfi_address bus when implementing DDR5 DFI?
and It will be mapped as SDR or DDR?