I meet some problems concerned to the timing between command read to read, write to write, read to write and write to read when changing chip select on DDR4. Could you help me to point out or confirm my understanding is correct or not?
1. As my understanding, JEDEC defined only the timing rtr, wtw, rtw, wtr in 2 cases: different bank group and same bank group. In the case different rank (chip select), it should be similar to different bank group, but data can do back-to-back plus a few cycle for preamble/crc latency.
This case, DFI/PHY also need more delay WHEN new command with different rank commencing on DFI, and WHEN that chip select asserted on bus (PHY_RDCSLAT, PHY_WRCSLAT). Maybe plus a few cycle by PHY_RDCSGAP, PHY_WRCSGAP if having
=> To keep data continuously, timing for rtr_cs/wtw_cs/rtw_cs/wtr_cs should be subtracted these delay (PHY_RDCSLAT, PHY_WRCSLAT, PHY_RDCSGAP, PHY_WRCSGAP). Is it correct?