DFI - ddr-phy.org

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DFI Phase Encoding

Hi,    The DFI spec does not specify about the phase encoding in detail for 1:2 and 1:4 systems . Is there any addendum document or any oth…

Started by Prasanna narasimha

1 May 10
Reply by John MacLaren

DDR5 CA bus mapping onto DFI address

Hi,DFI specs 5.0 is not clear to me in mapping CA bus onto DFI address for DDR5, What I found so far is the following: "For low power memor…

Started by Mohamed Rayan

1 Apr 8
Reply by Mohamed Rayan

DFI signals for DDR5

The following signals are listed in the DFI 5.0 specification as being required for DDR5 but it is not obvious what they would map to on th…

Started by Laurence Davies

0 Apr 5

Width of dfi_lp_*_wakeup signal in DFI 5.0

In Table 22 of the DFI 5.0 specification, the signals dfi_lp_ctrl_wakeup and dfi_lp_data_wakeup are defined as 4-bits wide. However, they a…

Started by Laurence Davies

2 Apr 5
Reply by Laurence Davies

LPDDR5 write interleaving feature

There is a special case write in the LPDDR5 DDR standard which requires insertion of a gap at the middle of the burst 32 write like the fol…

Started by Ramy Ahmed Ali

0 Apr 1

Two questions about Read Data Interface and Update Interface

Hello. I have an questio while designing PHY checking the DFI 5.0. 1) Seeing Figure 49, the values in PHY dfi_rddata are D0, D1, D2, D3, D4…

Started by Dongha Kim

3 Mar 27
Reply by Dongha Kim

DFI 5.0 read and write interface signaling and their clock domains

Hi, I would like to ask about the write/read interface signals (like "dfi_wrdata_en_p0,1,2,3") as they are synced to the DFI clock as per…

Started by Ramy Ahmed Ali

1 Mar 6
Reply by John MacLaren

DDR timing consecutive read/write or mix of them with different chip select

Hello everybody,  I meet some problems concerned to the timing between command read to read, write to write, read to write and write to rea…

Started by Victor

0 Feb 7

DDR4-MPSM-PDA

Hello, In MPSM entry with PDA mode, which exits first?  MPSM or PDA? Thanks in advance!

Started by Prateek

0 Jan 31

DFI data width

Hello, I'm new to this topic. Can you tell me why dfi write data bus width is generally twice the width of DRAM data bus? Is this because o…

Started by Prateek

1 Jan 24
Reply by John MacLaren

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