DFI - ddr-phy.org

Forum Discussions (211)

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Command Mapping in case of LPDDR5

Hi In case of LPDDR5, how does the command mapping happens if we are working on 1:4 mode? In my waveform, the complete command (MRR) along…

Started by Shikha Singh

0 Aug 7

Any update to DFI 5.0 for LPDDR5 Link ECC support?

Are there any updates to DFI 5.0 spec specifically related to LPDDR5 Link ECC support? Is there any ongoing discussions? If so, when is the…

Started by Deepti Sriramagiri

2 Jun 25
Reply by Deepti Sriramagiri

Is there a comparison between dfi5.0 and previous generations anywhere?

Can I find a discussion on the differences between 4.0 and 5.0 anywhere?

Started by Martin Kiernicki

0 Jun 12

dfi_wrdata_mask and dfi_rddata_dbi width

Hi All, I have few queries. Kindly help me. 1) It is written in spec that both dfi_wrdata_mask and dfi_rddata_dbi have width equal to DBI W…

Started by Abhishek Das

0 Apr 4

Disconnect protocol?

Hi, Can anyone explain me the objective of "DFI disconnect protocol [Sec 13.0]" from LP4 DFI specification? I read the section but could no…

Started by Dhaval shah

4 Mar 25
Reply by Uma Baskaran

Data bus mapping in matched frequency, 1:2 frequency ratio systems

For a matched frequency system, the DFI data width is defined as (generally) 2x the PHY data width, but I do not see any information that e…

Started by Andrew Nance

0 Feb 7

Update vs Training

Can anyone explain difference between purposes why phy initiates update and master protocols?"

Started by pradeep vetapalem

3 Dec 11, 2019
Reply by Atanu Biswas

PHY Master Interface based query

Hi, In the PHY Master Interface Description on page 63 of DFI spec its written that when requesting control of the DFI/DRAM buses, PHY wil…

Started by Atanu Biswas

1 Dec 9, 2019
Reply by John MacLaren

Query in DFI Spec Frequency Ratio operation

Hi all, I have a doubt in DFI Spec Page number 118. In the PHY side waveform for the read operation, dfi_rddata_en gets asserted at phase…

Started by Atanu Biswas

3 Dec 5, 2019
Reply by John MacLaren

dual channel in lpddr4

What is advantage of Dual channel in LPDDR4 ? We already have dual channels in our system with each channel having it's own PHY and MC. Wha…

Started by santhosh tej

1 Dec 2, 2019
Reply by harsha


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