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DFI 2.1 vs 3.0Hello, if I have a Controller that support only DDR3 and DFI 2.1.1 and a PHY which support dfi 3.0 could I connect toghether ? There is som… Started by Gianluigi Senise |
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10 hours ago Reply by Gianluigi Senise |
Query regarding dfi_rddata_en BUS slices in DFI 3.0Hi, On page 85, Figure 28, a relationship is shown between the slices of dfi_rddata_valid and dfi_rddata. What is not clear is, 1. Does t… Started by Sai Karthik Madabhushi |
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12 hours ago Reply by Sai Karthik Madabhushi |
Query regarding Tcmd_latHi, I have a query regarding Tcmd_lat in DFI 3.0. I am testing a DFI 3.0 interface with a DDR4 RAM and I am seeing the behaviour that Tcmd… Started by Sai Karthik Madabhushi |
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12 hours ago Reply by Sai Karthik Madabhushi |
DFI2.1/3.0 low power request assertionHi John, Is MC allowed to assert dfi_lp_req immediately after sending the last write data to PHY or it should wait for PHY to push out the… Started by Gyan Prakash |
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Jan 17 Reply by John MacLaren |
DFI 2.1/3.0 low power handshakeHi John, While inspecting the DFI 2.1/3.0 specification related to low power handshake, it is not clear whether MC is allowed to assert a n… Started by Gyan Prakash |
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Jan 17 Reply by John MacLaren |
Doubt about dfi_rddata_en_p0 timing in 1:2 Frequency Ratio modeHi, In DFI 3.0, Figure 43 "1:2 Frequency Ratio Single Read Data Example with Odd Read Data to Enable Timing", the value of parameter trdda… Started by qiannan |
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Jan 9 Reply by John MacLaren |
1:2 Frequency Ratio Figures PHY timing is misleadingLooking at Figure 42 "1:2 Frequency Ratio Single Read Data Example with Even Read Data to Enable Timing" in the DDR PHY Interface, Version… Started by John MacLaren |
0 | Dec 12, 2012 |
twrdata_delay definition inconsistency in Figure 33 of DFI 3.0In DFI 3.0, Table 7: twrdata_delay is defined as: Specifies the number of DFI clocks between when the dfi_wrdata_ensignal is asserted and w… Started by Patrick Twomey |
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Dec 12, 2012 Reply by John MacLaren |
Which devices require dfi_reset_n signal ?dfi_reset_n(_pN) has a note 6 (Used with LPDDR2 DRAM only.) from Figure 1 but a different description in Table 2. I hope Table description… Started by varma Devaganugula |
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Dec 12, 2012 Reply by John MacLaren |
width of dfi_wrdata_cs_n and dfi_rddata_cs_nhi, I see the width of dfi_wrdata_cs_n is mentioned as DFI Chip Select Width x DFI Data Enable Width while dfi_rddata_cs_n is only DFI Chi… Started by varma Devaganugula |
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Dec 12, 2012 Reply by John MacLaren |
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