Forum Discussions (206)
| Discussions | Replies | Latest Activity |
|---|---|---|
Update vs TrainingCan anyone explain difference between purposes why phy initiates update and master protocols?" Started by pradeep vetapalem |
3 |
Dec 11, 2019 Reply by Atanu Biswas |
PHY Master Interface based queryHi, In the PHY Master Interface Description on page 63 of DFI spec its written that when requesting control of the DFI/DRAM buses, PHY wil… Started by Atanu Biswas |
1 |
Dec 9, 2019 Reply by John MacLaren |
Query in DFI Spec Frequency Ratio operationHi all, I have a doubt in DFI Spec Page number 118. In the PHY side waveform for the read operation, dfi_rddata_en gets asserted at phase… Started by Atanu Biswas |
3 |
Dec 5, 2019 Reply by John MacLaren |
dual channel in lpddr4What is advantage of Dual channel in LPDDR4 ? We already have dual channels in our system with each channel having it's own PHY and MC. Wha… Started by santhosh tej |
1 |
Dec 2, 2019 Reply by harsha |
DFI READ FREQUENCY RATIO 1:2 Fig42/Fig43Hello there , Further clarification is required on the illustrations shown in figure 42 and figure 43 ( DFI 3.0 May 19 2012 ) . Why trd… Started by Nithin |
5 |
Sep 26, 2019 Reply by Divya |
dfi_init_complete signal assertion DFI4 and DDR4Hi, I'm new to DDR protocols. I want to know initialization condition of DDR4, when Memory Controller is sending dfi_init_start and when de… Started by Harish |
0 | Aug 23, 2019 |
Definition of tphy_wrlat for multi-cycle commands and/or 2N modeThe definition of tphy_wrlat is specified as: This parameter specifies the number of DFI PHY clock cycles from the time that a write comman… Started by Laurence Davies |
0 | Aug 1, 2019 |
DFI Phase EncodingHi, The DFI spec does not specify about the phase encoding in detail for 1:2 and 1:4 systems . Is there any addendum document or any oth… Started by Prasanna narasimha |
1 |
May 10, 2019 Reply by John MacLaren |
DDR5 CA bus mapping onto DFI addressHi,DFI specs 5.0 is not clear to me in mapping CA bus onto DFI address for DDR5, What I found so far is the following: "For low power memor… Started by Mohamed Rayan |
1 |
Apr 8, 2019 Reply by Mohamed Rayan |
DFI signals for DDR5The following signals are listed in the DFI 5.0 specification as being required for DDR5 but it is not obvious what they would map to on th… Started by Laurence Davies |
0 | Apr 5, 2019 |
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